1. Field of the Invention
The present invention relates generally to a display device. More particularly, this invention relates to a micromirror device with the pixel elements arranged in an array modulating an incident light with the modulation states of pixel elements display image data.
2. Description of the Related Art
After the dominance of CRT technology in the display industry for over 100 years, Flat Panel Displays (hereafter FPD) and Projection Displays have gained popularity because the FDP display implements a more compact image projecting system while projecting images on a larger display screen. Of several types of projection displays, projection displays using micro-displays are gaining recognition among the consumers because of their high picture quality and a lower cost than FPDs. There are two types of micro-displays used for projection displays on the market, i.e., micro-LCDs (Liquid Crystal Displays) and micromirror technology. Because the micromirror devices display images with an un-polarized light, the images projected by the micromirror device have a brightness superior to that of micro-LCDs, which use polarized light.
Even though there have been significant advances made in recent years in technologies implementing an electromechanical mirror device as a spatial light modulator (SLM), there are still limitations and difficulties when it is employed to display a high quality image. Specifically, when the images are digitally controlled, the image quality is adversely affected due to the fact that the images are not displayed with a sufficient number of gray scales.
An electromechanical mirror device implemented as the spatial light modulator (SLM) for an image projection apparatus has recently drawn a considerable amount of popular interest. The electromechanical mirror device commonly employs a relative large number of micromirrors configured as a “mirror array”. In general, the number of mirror elements ranges from 60,000 to several millions, placed on the surface of a substrate in an electromechanical mirror device.
Referring to FIG. 1A, an image display system 1 including a screen 2 is disclosed in a relevant U.S. Pat. No. 5,214,420. A light source 10 is used to generate light beams to project illumination for the display images on the display screen 2. The light 9 projected from the light source is further concentrated and directed toward lens 12 by way of mirror 11. Lenses 12, 13 and 14 form a beam columnator operative to columnate the light 9 into a column of light 8. A spatial light modulator 15 is controlled by a computer 19 through data transmitted over data cable 18 to selectively redirect a portion of the light from path 7 toward lens 5 to display on screen 2. FIG. 1B shows a SLM 15 that has a surface 16 that includes an array of switchable reflective elements 17, 27, 37, and 47, each of these reflective elements is attached to a hinge 30. When the element 17 is in an ON position, a portion of the light from path 7 is reflected and redirected along path 6 to lens 5 where it is enlarged or spread along path 4 to impinge on the display screen 2 to form an illuminated pixel 3. When the element 17 is in an OFF position, the light is reflected away from the display screen 2 and, hence, pixel 3 is dark.
The on-and-off states of the micromirror control scheme, as that implemented in the U.S. Pat. No. 5,214,420 and in most conventional display systems, impose a limitation on the quality of the display. Specifically, applying the conventional configuration of a control circuit limits the gray scale gradations produced in a conventional system (PWM between ON and OFF states), limited by the LSB (least significant bit, or the least pulse width). Due to the ON-OFF states implemented in the conventional systems, there is no way of providing a shorter pulse width than the duration represented by the LSB. The least quantity of light, which determines the gray scale, is the light reflected during the least pulse width. The limited levels of the gray scale lead to a degradation of the display image.
Specifically, FIG. 1C is a schematic circuit diagram to illustrate a control circuit implemented in a mirror element for controlling a micromirror according to U.S. Pat. No. 5,285,407. The control circuit includes memory cell 32. Various transistors are referred to as “M*” where “*” designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5, and M7 are p-channel transistors; transistors, M6, M8, and M9 are n-channel transistors. The capacitances, C1 and C2, represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a based on a Static Random Access Memory (SRAM) switch design. All access transistors M9 on a Row line receive a DATA signal from a different Bit-line 31a. The particular memory cell 32 is accessed for writing a bit to the cell by turning on the appropriate row select transistor M9, using the ROW signal functioning as a Word-line. Latch 32a consists of two cross-coupled inverters, M5/M6 and M7/M8, which permit two stable states that include a state 1 when is Node A high and Node B low, and a state 2 when Node A is low and Node B is high.
The control circuit positions the micro-mirrors to be at either an ON or an OFF angular orientation, as that shown in FIG. 1A. The brightness, i.e., the number of gray scales of display for a digitally control image system, is determined by the length of time the micro-mirror stays at an ON position. The length of time a micromirror is in an ON position is controlled by a multiple bit word. FIG. 1D shows the “binary time intervals” when controlling micromirrors with a four-bit word. As shown in FIG. 1D, the time durations have relative values of 1, 2, 4, 8, which in turn define the relative brightness for each of the four bits where “1” is the least significant bit and “8” is the most significant bit. According to the control mechanism as shown, the minimum controllable differences between gray scales for showing different levels of brightness is a represented by the “least significant bit” that maintains the micromirror at an ON position.
For example, assuming n bits of gray scales, one time frame is divided into 2″−1 equal time periods. For a 16.7-millisecond frame period and n-bit intensity values, the time period is 16.7/(2″−1) milliseconds.
Having established these times for each pixel of each frame, pixel intensities are quantified such that black is a 0 time period, the intensity level represented by the LSB is 1 time period, and the maximum brightness is 2″−1 time periods. Each pixel's quantified intensity determines its ON-time during a time frame. Thus, during a time frame, each pixel with a quantified value of more than 0 is ON for the number of time periods that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analog levels of light.
For controlling deflectable mirror devices, the PWM applies data to be formatted into “bit-planes”, with each bit-plane corresponding to a bit weight of the intensity of light. Thus, if the brightness of each pixel is represented by an n-bit value, each frame of data has the n-bit-planes. Then, each bit-plane has a 0 or 1 value for each mirror element. According to the PWM control scheme described in the preceding paragraphs, each bit-plane is independently loaded and the mirror elements are controlled according to bit-plane values corresponding to the value of each bit during one frame. Specifically, the bit-plane according to the LSB of each pixel is displayed for 1 time period.
FIG. 2 is an outline diagram showing the cross-section of a conventional mirror element.
As shown in FIG. 2, a plurality of pixel elements 610 is arrayed in a grid at each of the positions where vertically extended bit lines 621 and horizontally extended word lines 631 cross each other.
Each pixel element 610 comprises a mirror 611, which tilts freely, supported by a substrate (not shown in a drawing herein) by way of a hinge 613.
On the substrate, an ON electrode 615 and an OFF electrode 616 are symmetrically placed at positions sandwiching the hinge 613 between them.
The ON electrode 615, when a predetermined electric potential (noted simply as “potential” hereinafter) is applied thereto, attracts mirror 611 with a coulomb force and tilts it to a position abutting a stopper (not shown in a drawing herein). This causes incident light incident to the mirror 611 to be reflected to the light path of an ON position, which matches the optical axis of a projection optical system (not shown in a drawing herein).
The OFF electrode 616, when a predetermined potential is applied thereto, attracts mirror 611 with a coulomb force and tilts it to a position abutting a stopper equipped on the OFF side. This causes incident light incident to the mirror 611 to be reflected to the light path of an OFF position that is shifted from the optical axis of the above described projection optical system.
An ON capacitor 615a is connected to the ON electrode 615; it is also connected to a bit line 621-1 by way of a gate transistor 615b that is constituted by a field effect transistor (FET) or the like.
Furthermore, an OFF capacitor 616a is connected to the OFF electrode 616; it is also connected to a bit line 621-2 by way of a gate transistor 616b that is constituted by a field effect transistor (FET) or the like.
Opening and closing of the gate transistor 615b and gate transistor 616b are controlled through the word line 631.
Specifically, a single horizontal row of pixel elements 610 lined up with an arbitrary word line 631 is simultaneously selected, and the charging and discharging of capacitance to and from the ON capacitor 615a and OFF capacitor 616a is controlled by a bit line driver unit and a word line driver unit. Thereby the individual ON/OFF controls of the mirror 611 within the present single horizontal row are carried out.
In other words, the ON capacitor 615a and gate transistor 615b placed on the side where the ON electrode 615 is placed constitute a DRAM-structured memory cell M1.
Likewise, the OFF capacitor 616a and gate transistor 616b placed where the OFF electrode 616 is placed constitute a DRAM-structured memory cell M2.
With this configuration, the tilting operation for the mirror 611 is controlled in accordance with, for example, the presence and absence of data written to the respective memory cells of the ON electrode 615 and OFF electrode 616.
Incidentally, the configuration shown in FIG. 2 requires one mirror element with two drive circuits to be connected to two address electrodes.
This requirement creates a problem, however. The area occupied by the drive circuits that are connected to the respective address electrode are placed on the substrate. Therefore, if a very large number of mirror elements must be placed on the substrate, in order to produce a video image with a very high resolution, such as super high definition television (super HD TV), the area of the drive circuit occupying the substrate increases with the number of mirror elements. This eventually results in the need to enlarge the substrate itself and, thus, in a larger micromirror device at a high cost, which is a shortcoming of the configuration.